Espressif Systems /ESP32 /SPI0 /CACHE_SCTRL

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Interpret as CACHE_SCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (USR_SRAM_DIO)USR_SRAM_DIO 0 (USR_SRAM_QIO)USR_SRAM_QIO 0 (USR_WR_SRAM_DUMMY)USR_WR_SRAM_DUMMY 0 (USR_RD_SRAM_DUMMY)USR_RD_SRAM_DUMMY 0 (CACHE_SRAM_USR_RCMD)CACHE_SRAM_USR_RCMD 0SRAM_BYTES_LEN0SRAM_DUMMY_CYCLELEN 0SRAM_ADDR_BITLEN 0 (CACHE_SRAM_USR_WCMD)CACHE_SRAM_USR_WCMD

Fields

USR_SRAM_DIO

For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable

USR_SRAM_QIO

For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable

USR_WR_SRAM_DUMMY

For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.

USR_RD_SRAM_DUMMY

For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.

CACHE_SRAM_USR_RCMD

For SPI0 In the spi sram mode cache read sram for user define command.

SRAM_BYTES_LEN

For SPI0 In the sram mode it is the byte length of spi read sram data.

SRAM_DUMMY_CYCLELEN

For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

SRAM_ADDR_BITLEN

For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).

CACHE_SRAM_USR_WCMD

For SPI0 In the spi sram mode cache write sram for user define command

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